1. Field of the Invention
The present invention relates to a multiplier for multiplying three input signals or more, and more particularly, to a tripler for multiplying three input signals and a quadrupler for multiplying four input signals, both of which are formed on semiconductor integrated circuits and are operable under a low power source voltage such as 3 V or less.
2. Description of the Prior Art
A conventional tripler is composed of a differential circuit and emitter-coupled pairs of bipolar transistors whose collectors are cross-coupled with each other. The emitter-coupled pairs are cascaded at a multistage and the differential circuit is connected in series to the first or last stage of the emitter-coupled pairs.
A conventional quadrupler is similar in configuration to the conventional tripler described above excepting that an additional emitter-coupled pair is provided.
One of the conventional triplers is disclosed in detail in IEEE Journal of Solid-State Circuits, VOL. SC-16, NO.4, pp.392-399, May 1981, which is shown in FIG. 1.
As shown in FIG. 1, the conventional tripler TP20 contains a first pair of npn bipolar transistors Q21 and Q22, a second pair of npn bipolar transistors Q23 and Q24, a third pair of npn bipolar transistors Q25 and Q26, a fourth pair of npn bipolar transistors Q27 and Q28, a fifth pair of npn bipolar transistors Q29 and Q30, and a constant current source CS0 current: I.sub.0).
In a first stage, emitters of the transistors Q21 and Q22 are coupled together and emitters of the transistors Q23 and Q24 are coupled together. Collectors of the transistors Q21 and Q23 are connected to each other and collectors of the transistors Q22 and Q24 are connected to each other.
A differential output current .DELTA.I.sub.OUT20 of the tripler TP20 is derived from the collectors thus connected of the transistors Q21 and Q23 and those of the transistors Q22 and Q24.
Bases of the transistors Q22 and Q23 are coupled together, and bases of the transistors Q21 and Q24 are coupled together. A first input voltage V.sub.1 is applied across the coupled bases of the transistors Q22 and Q23 and those of the transistors Q21 and Q24.
In a second stage, similarly, emitters of the transistors Q25 and Q26 are coupled together and emitters of the transistors Q27 and Q28 are coupled together. Collectors of the transistors Q25 and Q27 are connected to each other and collectors of the transistors Q26 and Q28 are connected to each other. The coupled collectors of the transistors Q25 and Q27 are connected to the coupled emitters of the transistors Q21 and Q22. The coupled collectors of the transistors Q26 and Q28 are connected to the coupled emitters of the transistors Q23 and Q24.
Bases of the transistors Q25 and Q28 are coupled together and bases of the transistors Q26 and Q27 are coupled together. A second input voltage V.sub.2 is applied across the coupled bases of the transistors Q26 and Q27 and those of the transistors Q25 and Q28.
In a third stage, emitters of the transistors Q29 and Q30 are coupled together to be connected to the constant current source CS0. Bases of the transistors Q29 and Q30 are applied with a third input voltage V.sub.3. A collector of the transistor Q29 is connected to the coupled emitters of the transistors Q25 and Q26. A collector of the transistor Q30 is connected to the coupled emitters of the transistors Q27 and Q28.
The third, fourth and fifth emitter-coupled pairs of the transistors Q25, Q26, Q27, Q28, Q29 and Q30 constitute the well known Gilbert multiplier cell. Therefore, it can be said that the conventional tripler TP20 in FIG. 1 is composed of the multiplier and first and second emitter-coupled pairs whose collectors are crossly coupled with each other.
An output differential current .increment.I.sub.20 of the Gilbert multiplier cell MP20 is taken out from the coupled collectors of the transistors Q25 and Q27 and those of the transistors Q26 and Q28.
The output differential current .increment.I.sub.OUT20 of the tripler TP20 is expressed by the following equation (1) as ##EQU1##
In the equation (1), .alpha..sub.Fn is the dc common-base current gain factor of an npn bipolar transistor, and V.sub.T is the thermal voltage that is expressed as V.sub.T =kT/q where k is Boltzmann's constant, T is absolute temperature in degrees Kelvin and q is the charge of an electron.
The differential output current .increment.I.sub.20 of the Gilbert multiplier cell MP20 is expressed by the following equation (2) as ##EQU2## Therefore, the output differential current .increment.I.sub.OUT20 of the tripler TP20 can be expressed by the following equation (3) as ##EQU3##
Here, since tanhx can be approximated in small signal applications as tanhx=x-(1/3)x.sup.3 . . . .apprxeq.X (.vertline.x.vertline.&lt;&lt;1), the current .increment.I.sub.OUT20 can be rewritten as the following equation (4) ##EQU4##
It is seen from the equation (4) that the differential output current .increment.I.sub.OUT20 of the conventional tripler TP20 shown in FIG. 1 is proportional to the product or multiplication result of the three input voltages V.sub.1, V.sub.2 and V.sub.3.
Since the conventional tripler TP20 has three vertically stacked stages of the bipolar transistors, the tripler TP20 needs at least about 4 V for the power source voltage to operate stably.
Next, one of the conventional quadruplers is disclosed in U.S. Pat. No. 4,694,204, which is shown in FIG. 2.
As shown in FIG. 2, the conventional quadrupler QP21 contains a first pair of npn bipolar transistors Q31 and Q32, a second pair of npn bipolar transistors Q33 and Q34, a third pair of npn bipolar transistors Q35 and Q36, a fourth pair of npn bipolar transistors Q37 and Q38, a fifth pair of npn bipolar transistors Q39 and Q40, a sixth pair of npn bipolar transistors Q41 and Q42, a seventh pair of npn bipolar transistors Q43 and Q44, and a constant current source CS0' (current:I.sub.0).
In a first stage, emitters of the transistors Q31 and Q32 are coupled together and emitters of the transistors Q33 and Q34 are coupled together. Collectors of the transistors Q31 and Q33 are connected to each other and collectors of the transistors Q32 and Q34 are connected to each other.
An output differential current .increment.I.sub.OUT21 of the quadrupler QP21 is taken out from the collectors thus connected of the transistors Q31 and Q33 and those of the transistors Q32 and Q34.
Bases of the transistors Q32 and Q33 are coupled together and bases of the transistors Q31 and Q34 are coupled together. A first input voltage V.sub.1 is applied across the coupled bases of the transistors Q32 and Q33 and those of the transistors Q31 and Q34.
In a second stage, similarly, emitters of the transistors Q35 and Q36 are coupled together and emitters of the transistors Q37 and Q38 are coupled together. Collectors of the transistors Q35 and Q37 are connected to each other and collectors of the transistors Q36 and Q38 are connected to each other. The coupled collectors of the transistors Q35 and Q37 are connected to the coupled emitters of the transistors Q31 and Q32. The coupled collectors of the transistors Q36 and Q38 are connected to the coupled emitters of the transistors Q33 and Q34.
Bases of the transistors Q35 and Q38 are coupled together and bases of the transistors Q36 and Q37 are coupled together. A second input voltage V.sub.2 is applied across the coupled bases of the transistors Q36 and Q37 and those of the transistors Q35 and Q38.
In a third stage, emitters of the transistors Q39 and Q40 are coupled together and emitters of the transistors Q41 and Q42 are coupled together. Collectors of the transistors Q39 and Q41 are connected to each other and collectors of the transistors Q40 and Q42 are connected to each other. The coupled collectors of the transistors Q39 and Q41 are connected to the coupled emitters of the transistors Q35 and Q36. The coupled collectors of the transistors Q40 and Q42 are connected to the coupled emitters of the transistors Q37 and Q38.
Bases of the transistors Q39 and Q42 are coupled together and bases of the transistors Q40 and Q41 are coupled together. A third input voltage V.sub.3 is applied across the coupled bases of the transistors Q39 and Q42 and those of the transistors Q40 and Q41.
In the fourth stage, emitters of the transistors Q43 and Q44 are coupled together to be connected to a constant current source CS0' (current:I.sub.0). Bases of the transistors Q43 and Q44 are applied with a fourth input voltage V.sub.4. A collector of the transistor Q43 is connected to the coupled emitters of the transistors Q39 and Q40. A collector of the transistor Q44 is connected to the coupled emitters of the transistor Q41 and Q42.
The third, fourth, fifth, sixth and seventh emitter-coupled pairs of the transistors Q35, Q36, Q37, Q38, Q39, Q40, Q41, Q42, Q43 and Q44 constitute a tripler TP21 that is the same in configuration as the conventional tripler TP20 shown in FIG. 1. Therefore, it can be said that the conventional quadrupler QP21 in FIG. 2 is composed of the conventional tripler TP20 shown in FIG. 1 and the first and second emitter-coupled pairs whose collectors are crossly coupled with each other.
An output differential current .increment.I.sub.21 of the tripler TP21 is taken out from the coupled collectors of the transistors Q35 and Q37 and those of the transistors Q36 and Q38.
The output differential current .increment.I.sub.OUT21 of the quadrupler QP21 is expressed by the following equation (1') as ##EQU5##
The differential output current .increment.I.sub.21 of the tripler TP21 in the equation (1') is expressed by the following equation (5) as ##EQU6##
Therefore, the differential output current .increment.I.sub.OUT21 of the quadrupler QP21 is expressed by the following equation (6) as ##EQU7##
Here, since tanhx can be approximated in small signal applications as tanhx=x-(1/3)x.sup.3 . . . .apprxeq.X (.vertline.x.vertline.&lt;&lt;1), .increment.I.sub.OUT can be rewritten to the following equation (7) as ##EQU8##
It is seen from the equation (7) that the differential output current .increment.I.sub.OUT21 of the conventional quadrupler QP21 shown in FIG. 2 is proportional to the product of the four input voltage V.sub.1, V.sub.2, V.sub.3 and V.sub.4.
Since the conventional quadrupler QP21 shown in FIG. 2 has four vertically stacked stages of the bipolar transistors, the quadrupler QP21 needs at least about 5 V for the power source voltage to operate stably.